Radar circuits often use a phase-locked loop (PLL) to generate a ramp modulated signal. In the case of a PLL with a charge pump, the charge pump is used to drive a control port of a voltage controlled oscillator (VCO). When fabricated by way of a BICMOS millimeter wave fabrication process, the voltage range of the varactor within the VCO can extend beyond the maximum voltage tolerated by the (high-speed) output bipolar transistor of the charge pump. Accordingly, in order to maximize the frequency coverage of the PLL, the output voltage of the charge pump must exceed the maximum voltage of the charge pump transistors.
FIG. 1 illustrates a simplified circuit diagram of a charge pump circuit 100. The charge pump circuit 100 consists of a pair of bipolar transistors 110, 120 having emitter terminals coupled to a pulse current source 130. A collector terminal of the first bipolar transistor 110 is coupled to a trickle current source 140 and to an output node 105 of the charge pump circuit 100. A collector terminal of the second bipolar transistor 120 is coupled to a supply rail 150. A first voltage control signal 115 is received at a base terminal of the first bipolar transistor 110, and is arranged to control the switching of the first bipolar transistor 110. A second voltage control signal 125 is received at a base terminal of the second bipolar transistor 120, and is arranged to control the switching of the second bipolar transistor 120.
In operation, the first voltage control signal 115 is generated to control the first bipolar transistor 110 such that when the first bipolar transistor 110 is ‘off’ the trickle current from the trickle current source 140 flows through the output node 105 of the charge pump circuit 100. Conversely, when the first bipolar transistor 110 is ‘on’, the current flowing to the output node 105 will equal the difference between the pulse current from the pulse current source 130 and the trickle current from the trickle current source 140.
The second voltage control signal 125 is generated to control the second bipolar transistor 120 to provide a current path for the pulse current from the pulse current source 130 when the first bipolar transistor 110 is off, in order to allow the pulse current source 130 to always be on. Accordingly, the first and second voltage control signals 115, 125 may be viewed as differential voltage signals arranged to control the first and second bipolar transistors 110, 120 in a differential manner.
The voltage signals 115, 125 received at the base terminals of the bipolar transistors 110, 120 are generated by way of respective first and second current signals 112, 122 injected into the voltage signal nodes and a resistance network 160 coupled between the voltage signal nodes and a reference voltage (e.g. ground).
In the case of a PLL fabricated by way of a BICMOS millimeter wave fabrication process, the full voltage range for driving the varactor within the VCO might be, for example, 0.4V to 4.5V. Accordingly, in order to maximize the frequency coverage of the PLL, the charge pump circuit 100 should be capable of generating an output voltage Vout of a corresponding range: 0.4V to 4.5V. In particular, the charge pump circuit 100 should be able to generate a ramped output voltage signal whereby during the ‘ramp up’ phase the voltage at the output node 105 increases up to the maximum output voltage of 4.5V, whilst during ‘the ramp down’ phase the voltage at the output node 105 decreases down to the minimum output voltage of 0.4V. The voltage signal at the output node 105 is achieved by generating current pulses at the output node 105 that are converted into a voltage signal by a filter (not shown).
However, the BICMOS millimeter wave bipolar transistors 110, 120 are unable to tolerate voltage levels as high as 4.5V, and may be limited to voltage levels of, for example, 3.9V or less. Accordingly, in order to achieve the high-end output voltage level of 4.5V at the output node 105, the voltage at the emitter terminal of the first bipolar transistor 110 must be at least 0.6V in order to limit the voltage across the first bipolar transistor 110 to 3.9V. Such a high voltage level at the emitter terminal of the first bipolar transistor would result in a minimum achievable output voltage Vout at the output node 105 of 0.8V.